Progress on the Tritium Project
I haven’t been able to work on this project much since I haven’t had the money to get the parts and PCBs manufactured. I’m currently working on creating the memory and I designed and ordered the PCBs for a rising edge triggered master-slave D tri-flop to see if that works and if it does, I’ll see about moving on to actually design the architecture. I’ll talk to some local college professors to see the best way about designing the architecture but I think the hardest part would be the control unit due to the sheer amount of gates and PCB space needed for a pure balanced ternary decoder.
Control Unit Dilemma
The control unit is proving quite troublesome to conceputalize if I wanted the prototype to be one clock cycle per instruction. I think I might end up using a binary EEPROM as a lookup table similar to what Ben Eater has done in his 8-bit computer series and using ternary to binary encoders/decoders since it’d take so much board space and so many transistors to design that in hardware.
Instruction Set Architecture Dilemma
I’m still deciding on the ISA as well since I don’t think I’ll keep the original Tritium-6 ISA I wrote up a while ago. I might end up making the instructions 2-words wide so I have more freedom in the instructions but that’d require a more complex decoder and more complex execution cycle to load the two words instead of one. I’ll talk to some people that are smarter than me about proper ISA design since I have no experience in it.